The present invention is generally related to the field of semiconductor devices. More particularly, the present invention is related to memory cells in semiconductor devices.
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash memory devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash memory devices enable the erasing of all memory cells in the device using a single current pulse.
Product development efforts in flash memory devices have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times, reducing cell dimensions, and optimizing dielectric materials used in memory cells. In fabrication of flash memory cells utilizing floating gate flash memory technology, one important dielectric material is a thin gate oxide layer (also referred to as a tunnel oxide layer), which is situated between a floating gate and a silicon substrate. For optimal flash memory cell performance, it is desirable to have a thin tunnel oxide layer that also has a substantially uniform thickness between the floating gate and the silicon substrate.
During fabrication of a floating gate memory cell, such as a floating gate flash memory cell, a tunnel oxide layer is formed on a silicon substrate. A stacked gate structure comprising a floating gate, an Oxide-Nitride-Oxide (ONO) stack, and a control gate (also referred to as a word line) is then formed on the tunnel oxide layer. The stacked gate structure is then patterned by, for example, masking and etching the stacked gate structure. During etching of the stacked gate structure, the underlying tunnel oxide layer is also etched, resulting in exposed sides of the tunnel oxide layer. Consequently, during subsequent thermal oxidation steps utilized in the formation of the floating gate flash memory cell, oxygen can diffuse into end regions of the tunnel oxide layer and cause the end regions to grow thicker. The thickening of the end regions of the tunnel oxide layer discussed above is herein referred to as xe2x80x9clateral oxide encroachment.xe2x80x9d The thickening of the end regions of the tunnel oxide layer is also colloquially referred to as a xe2x80x9cbird""s beakxe2x80x9d profile.
As a result of thickening of the end regions of the tunnel oxide layer discussed above, performance of the floating gate memory cell can be undesirably diminished. For example, the thicker end regions of the tunnel oxide layer can decrease floating gate erase uniformity and floating gate memory cell reliability by inhibiting erase current and causing the erase current to be concentrated through thinner portions of the tunnel oxide layer. Furthermore, if the control gate width is sufficiently narrow, e.g. at a control gate width of approximately 0.25 microns, the xe2x80x9cbird""s beakxe2x80x9d profiles that form at end regions of the tunnel oxide layer can join in the middle of the tunnel oxide layer, causing an undesirable overall increase of tunnel oxide layer thickness. The overall increase in tunnel oxide layer thickness can reduce performance and reliability of the floating gate memory cell.
In one attempt to reduce the xe2x80x9cbird""s beakxe2x80x9d profile discussed above, semiconductor memory manufacturers have reduced the thermal budget for oxide deposition. However, this attempted solution to the xe2x80x9cbird""s beakxe2x80x9d formation problem can result in an insufficient amount of oxide being deposited to adequately protect the silicon surface of the wafer. Additionally, the attempted solution discussed above can also result in an oxide of an insufficient quality to adequately protect the wafer""s silicon surface.
Thus, there is a need in the art for a floating gate memory cell having increased performance and reliability.
The present invention is directed to structure and method for suppressing oxide encroachment in a floating gate memory cell. The present invention addresses and resolves the need in the art for a floating gate memory cell having increased performance and reliability.
According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises a tunnel oxide layer, where the tunnel oxide layer is situated on the substrate. The structure further comprises a floating gate situated on the tunnel oxide layer, where the floating gate comprises nitrogen. The floating gate may further comprise polysilicon and may be situated in a floating gate flash memory cell, for example. The nitrogen may suppress oxide growth at first and second end regions of the tunnel oxide layer, for example. The nitrogen may be implanted in the floating gate, for example, at a concentration of between approximately 1013 atoms per cm2 and approximately 1015 atoms per cm2.
According to this exemplary embodiment, the structure further comprises an ONO stack situated over the floating gate. The structure may further comprise a control gate situated over the ONO stack. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.